This invention relates generally to semiconductor devices and more particularly to high-k dielectric transistor gate structures and methods for fabricating the same.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact or electrode is energized to create an electric field in a channel region of a semiconductor body, by which current is allowed to conduct between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric or gate oxide, such as silicon dioxide (SiO2), is formed over the channel region, typically by thermal oxidation. A gate electrode or gate contact (e.g., metal or doped polysilicon) is then formed over the gate dielectric, and the gate dielectric and gate electrode materials are then patterned to form a gate structure overlying the channel region of the substrate.
The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate electrode, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface.
However, there are electrical and physical limitations on the extent to which thickness of gate dielectrics formed of SiO2 can be reduced. For example, very thin SiO2 gate dielectrics are prone to large gate tunneling leakage currents resulting from direct tunneling through the thin gate oxide. In addition, there are conventional limitations on the ability to form such thin oxide films with uniform thickness. Furthermore, thin SiO2 gate dielectric layers provide a poor diffusion barrier to dopants, for example, and may allow high boron dopant penetration into the underlying channel region of the silicon during fabrication of the source/drain regions.
Recent efforts directed to MOS device scaling have accordingly focused on high-k dielectric materials having dielectric constants greater than that of SiO2, which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. The relative performance of these high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2. Because the dielectric constant is higher, a thicker high-k dielectric layer can be deposited to avoid or mitigate tunneling leakage currents, while still achieving the required value of EOT that is comparable to the EOT value of a thinner layer of thermally grown SiO2.
High-k dielectrics are sometimes deposited directly over a silicon substrate to form a gate dielectric layer using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes, wherein oxygen and/or nitrogen in the material reacts with the silicon at the interface. The performance and reliability of the resulting transistors, in turn, is dependent upon the quality of the high-k dielectric material in the bulk of the gate dielectric as well as the quality of the interface region between the high-k gate dielectric material and the underlying silicon. Thus, there is a need for improved gate structures and fabrication techniques by which high quality gate dielectrics and interfaces can be achieved using high-k dielectric materials.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention relates to high-k transistor gate structures and fabrication methods therefor, in which the gate dielectric interface region near the semiconductor substrate is essentially denuded of nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration. The inventors have appreciated that providing uniform nitrogen concentrations in the bulk high-k dielectric operates to impede or block diffusion of boron or other impurities implanted in an overlying gate contact or electrode material, while also stabilizing the high-k material. At the same time, preventing large nitrogen concentrations in the interface portion of the gate dielectric structure inhibits mobility degradation and other performance problems in the resulting transistors.
In one aspect of the invention, transistor gate structures and gate dielectric structures therefor are provided, wherein the dielectric structure comprises a bulk portion and an interface portion. The bulk portion comprises a high-k dielectric material with a nitrogen concentration of about 3 atomic percent or more and a nitrogen concentration variation of about 4 percent or less, such as 3 percent or less in one example. The interface portion comprises dielectric material between the bulk portion and the semiconductor body with a nitrogen concentration of about 3 atomic percent or less, wherein the interface is about 3 monolayers thick or less in one example. The high-k dielectric nitrogen concentration may be made as high as desired to provide a barrier against boron diffusion into the underlying semiconductor body, such as up to about 40 atomic percent in one example. The high-k dielectric material in the bulk portion may be any high-k dielectric, for example, a metal silicon oxynitride comprising a metal such as Zr, Hf, La, Y, Gd, Eu, Pr, or Ce. In one implementation illustrated and described below, the nitrided high-k dielectric material of the bulk portion is hafnium silicon oxynitride (HfSiON).
In another aspect of the invention, methods are provided for forming a transistor gate structure, comprising depositing HfSiO over the semiconductor body using a chemical vapor deposition process, introducing nitrogen into the high-k dielectric material using a plasma nitridation process, and annealing the nitrided high-k dielectric material. A gate electrode layer is then formed over the bulk portion of the dielectric structure, and the gate electrode layer and the dielectric structure are patterned to provide a transistor gate structure. In one example illustrated and described below, the high-k dielectric material is HfSiON including an interface portion over the semiconductor body having a nitrogen concentration of about 3 atomic percent or less, as well as a bulk high-k portion over the interface with a nitrogen concentration of about 3 atomic percent or more and a nitrogen concentration variation of about 4 atomic percent or less.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.